Hypothesis: Zen 4 (EPYC 4 “Genoa”, Ryzen 7000)


New socket for Zen4 Epyc/TR/Ryzen is a given, and in addition confirmed by the Milan presentation (Genoa will use SP5)

https://www.anandtech.com/present/13490/cadence-and-micron-ddr5-update

Introducing DDR5 in 2021 with new sockets for all the lineup is the following step. Additionally, PCIe5 is prone to be in there, too. The spec was completed in Could 2019, and it appears to take ~2 years from that time to {hardware} on cabinets (PCIe4 Oct2017/ AM4 Zen2 in 2019), additionally lining up for 2021.

New socket additionally means not having to cope with preexisting contraints like Zen2’s chiplet paradigm needed to do with to keep up AM4/SP3 compatibility. So I would suppose there might be some additional advances on this space with interposers or extra inventive chiplet makes use of.

I additionally agree Zen4 will go wider to enhance efficiency whereas additionally persevering with Zen/Zen+/Zen2’s path in direction of getting ever nearer to the sensible ~5GHz restrict on extra cores. Zen2’s enhance algorithm will evolve to be much more efficient at getting 100% out of every particular person piece of silicon out of the fab.

I anticipate AVX-512 help in Zen4, identical to Zen/Zen+ supported AVX/2: be appropriate, however execute at half charge. So far as I perceive AVX512 is good to have from an directions perspective, aside from the throughput enhance if one had been to do a full charge implementation of it. If it occurs, I’m wondering which circles of AVX-512 compatibility hell will they help.

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Additionally, AMD appreciated the sport across the quantity 7 for Zen2’s launch (even going to a launch on a Sunday, and launching merchandise on the seventh of every month), so that is one other ultimate meme worthy launch for them. Blatantly stolen from the web hivemind:

  • AM5 + Zen4 (simply rename it to Zen5, lol)
  • DDR5
  • PCIe 5.0
  • Utilizing some type of TSMC’s 5nm node?
  • Launching 5/5/2021 (2021 = 2+2+1 = 5)

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edit: Simply had a thought.

I bear in mind studying that AM4 was considerably constrained in what capabilites it uncovered out of the Zeppelin SOC whereas sustaining compatiblity with faildozer components. Motherboard distributors had been pessimistic about it from the beginning contemplating the earlier 5 years of AMD’s historical past.

For instance, Zeppelin had 32 PCIe lanes in it, solely 24 had been used for AM4.

This time it is a clear slate for greatness contemplating what Zen has sparked within the business, to not point out the gross sales. Everybody can be prepared to do attention-grabbing issues with it, or go the additional mile on connectivity.

If AM5 does some inventive chiplet utilization or strikes to an interposer, I would like to see an APU with an HBM2/3 stack in there. That will be superior, both as one other cache stage for common utilization or to present the iGPU some juicy bandwidth to work with.



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